1. Field of the Invention
The present invention relates to integrated circuit technology. More particularly, the present invention relates to apparatus and methods for implementing walkout of device junctions in an integrated circuit.
2. The Prior Art
In non-volatile memory integrated circuits such as flash memory and EEPROM memory integrated circuits, a high-voltage charge pump circuit is used to generate high voltage for programming and erasing operations. A circuit is used to set the high-voltage charge pump output at an optimized voltage level best for the programming and erasing operations.
Memory cell margins are important considerations. An “off” cell has a high threshold voltage (for example, +2V), and an “on” cell has a low threshold voltage (for example, −2V). If a sense amplifier has a reference voltage of 0V, then the margin for an “off” cell is 2V−0V=2V, and the margin for “on” cell is 0V−2V=−2V. If the clamped high-voltage level is too low, a non-volatile memory cannot be programmed or erased well and as a result, margins for both “on” cells and “off” cells will be poor. A weakly programmed “on” cell may have threshold voltage of −0.5V, and the margin for that “on” cell is only 0V−0.5V=−0.5V. A weakly erased “off” cell may have threshold voltage of +0.5V and the margin for that “off” cell is only 0.5V−0V=0.5V.
Endurance is defined as the number of programming and erasing cycles that can be performed before the margin window collapses, that is, the margins for both “off” and “on” cells become so small that the sense amplifier can no longer sense whether the cell is “off” or “on.” The endurance of a memory cell will be poor if the margins for both “off” and “on” cells are poor.
Data retention is defined as the number of years a memory cell can keep its charge and maintain appropriate margins to be correctly sensed by the sense amplifier. If the high voltage level to which the programming and erasing charge pump has been set is too high, the margins for both “off” and “on” cells may be better but data retention may be worse. This is because the thin oxide through which programming takes place may be damaged by the high electric field present during program and erase operations and a leakage path may be generated causing data loss. A well-controlled and optimized high-voltage clamp level is needed in order for the memory to have both good endurance and good data retention.
In the prior art, the oxides used for tunneling or for hot electron injection may be fabricated thinner to achieve better margins, but thinner oxides are more susceptible to damage from exposure to high electric fields. Consequently, endurance is better but data retention is worse. If oxides for tunneling or for hot electron injection are fabricated thicker to achieve better data retention, the high-voltage level to which the programming and erasing charge pump is clamped needs to be higher in order to program or erase through the thicker oxide. If the clamped high voltage is too high, and exceeds the breakdown voltage of the transistor devices that are exposed to it, leakage may occur in these devices causing a high-voltage flip-flop to flip to an opposite, incorrect state, or cause other misoperations. In addition, if the clamped high voltage level is too high, the critical oxide layers through which programming and erase operations are conducted are more susceptible to damage from exposure to high electric fields. As a result, data retention may suffer.